The invention relates to techniques and structures for front-surface gettering of impurities in integrated circuits.
It should be noted that the precise mechanisms involved in gettering are not well understood, and numerous technical articles have been written directed to this subject setting forth various, sometimes inconsistent, theories.
So-called "gettering" techniques introduce low energy sites into a semiconductor crystal lattice structure so that at high temperatures, various fast diffusing impurities, especially heavy metallic impurities such as copper, iron, and gold will be trapped. It is highly desirable in semiconductor devices to trap such heavy metallic impurities in locations remote from the "active" regions of semiconductor devices because otherwise such metallic impurities represent minority carrier sites that result in frequent generation and recombination of minority carriers in the active regions. Such generation and recombination of minority carriers in active regions of a transistor produces noise in currents flowing through the transistor. Such noise includes the type sometimes referred to as "popcorn" noise or "burst" noise, and also includes 1/f noise, both of which ae highly undesirable in semiconductor devices such as JFETs and NPN transistors, etc. that are used in high gain, low noise amplifier circuits. Various techniques have been proposed or utilized for gettering unwanted impurities from semiconductors. Such techniques have included introducing highly stressed or damaged regions in the semiconductor single crystal lattice structure by diffusing or implanting ions into front and/or back surfaces of integrated circuit wafers. Such damage produces low energy sites in the semiconductor lattice structure that act as traps for fast diffusing metallic impurities when the semiconductor wafer temperature is elevated to appropriate gettering temperatures.
Perhaps the closest prior art is indicated by U.S. Pat. No. 3,874,936 and by "Gettering Technique and Structure", by Bogardus, et al., IBM Technical Disclosure Bulletin Vol. 16, No. 4, September, 1983, page 1066. U.S. Pat. No. 3,874,936 discloses creating top surface stressed areas on a semiconductor wafer by providing boron diffusions within both N+ emitter regions and N+ collector contact regions in NPN transistors. The Bogardus disclosure shows the technique of creating highly damaged ring-shaped regions in the base and collector regions of NPN transistors to provide top surface gettering of impurities in an integrated circuit structure. The disclosed techniques require steps additional to those of standard integrated circuit processes, adding considerably to the cost of manufacture of the integrated circuits. The above references teach that the gettering achieved reduces the occurrence of "soft" PN junctions and increases yields. The references do not teach that use of front-surface gettering of any kind is practical as a means of reducing the noise of bipolar transistors, field effect transistors, or integrated circuits containing such devices.
It is thought that the prior art includes bipolar transistor devices in which N+ rings have been utilized in the collector region for the purpose of reducing series collector resistance. It also is believed that the prior art includes NPN transistor structures in which N+ rings have been formed within the base region and electrically shorted thereto for the purpose of reducing minority carrier storage time to increase transistor switching speeds.
There is an unmet need for an improved technique of substantially reducing the noise produced in integrated circuits manufactured by conventional integrated circuit manufacturing processes without substantially increasing the number of processing steps or the cost of the overall manufacturing process. For example, the assignee has experienced yield losses of two to five percent of certain low noise operational amplifier circuits and the like due to failure to pass low frequency noise tests.